Executive brief
A hardware flaw in several Arm-based processors can cause the Linux kernel to incorrectly manage memory updates. This could potentially allow a local attacker to bypass memory protections or cause system instability by exploiting a timing issue in how the processor clears its internal memory address cache. The issue has been addressed by a software update that forces the processor to double-check these memory operations.
Technical details
A hardware erratum in multiple Arm CPUs (including Cortex-A76, A77, A78, A710, X1, and X2 variants) causes broadcast TLB Invalidation (TLBI) and Data Synchronization Barrier (DSB) sequences to complete before the global observation of writes translated by the affected TLB entry. While the TLB entries themselves are removed correctly, memory accesses translated by the invalidated entry may not be globally observed in the correct order. The mitigation, ARM64_WORKAROUND_REPEAT_TLBI, implements a repeat of the TLBI;DSB sequence to ensure all memory write effects are globally observed. This is a local vulnerability requiring the ability to execute code on the affected arm64 system.
Affected products
- Linux Linux Kernel arm64 architecture; various versions prior to 2026-06 patches
Timeline
- 2026-06-16: other: Patch authored by Mark Rutland
- 2026-06-19: patched: Patches committed to stable kernel trees
- 2026-07-01: disclosed: CVE-2026-53354 published
References
- https://git.kernel.org/stable/c/1268c64e2bcb6e968152990e87bd10c440fcc9c0
- https://git.kernel.org/stable/c/1b47b1e1d8675fdf5f6e11e7fa19c704d8c6f5cd
- https://git.kernel.org/stable/c/4e7c80742e6dada9f8b9ad63f3a49c03af07ecb8
- https://git.kernel.org/stable/c/7c3ad9365079e716b57d2363d3081ee7680cc18e
- https://git.kernel.org/stable/c/8364384ae82fbffdf8968abaac3455ed854da18d
- https://git.kernel.org/stable/c/925058203229403008d77a52b1e63e2ae5f4a3cf
- https://git.kernel.org/stable/c/cfd391e74134db664feb499d43af286380b10ba8