CVE-2025-51679: openRISC OR1200 RTL-to-netlist mismatch in program counter

CVE-2025-51679 · Severity: critical · CVSS 9.1 · Published 2026-08-26

The openRISC OR1200 processor is an open-source CPU core used in embedded systems and SoCs. A design flaw causes a mismatch between the register-transfer level (RTL) design and synthesized hardware, resulting in incorrect program counter updates and undefined instruction execution. This can cause the processor to stall, fetch wrong instructions, or execute from incorrect memory addresses, disrupting all dependent systems.

Technologies: OpenRISC OR1200. Vendors: OpenRISC.

Quick answers

Is CVE-2025-51679 exploited in the wild?
No. Junglewise Threat Intelligence has no report of CVE-2025-51679 being exploited in the wild.
How severe is CVE-2025-51679?
Critical severity, with a CVSS score of 9.1, published 26 August 2026.
Which products and versions are affected?
OpenRISC OR1200 commit 83ac6b42d73f00daa88a996a1f6738d5a639a105.
Is there a fix for CVE-2025-51679?
No fixed version is recorded yet. Check the vendor's advisory in the references below. If you run it, Junglewise drafts a mitigation that fits your setup and applies it once you approve, with senior security engineers behind it.
How is CVE-2025-51679 attacked?
It is attacked with local access.
Am I affected by CVE-2025-51679?
Check whether you run OpenRISC OR1200 at an affected version. Junglewise does that check for you around the clock: connect your code, cloud and domains, and it matches new vulnerabilities like this one against what you actually run and tells you when one reaches you.

Technical details

The vulnerability is a hardware design flaw (CWE-1281: Improper Validation of Specified Quantity in Input) in the OR1200 processor's program counter (PC) update logic. The root cause is an inaccurate update of PC values when the Next Program Counter (NPC) stored in Special Purpose Registers (SPRs) changes; the PC becomes stalled at its previous value instead of advancing. Additionally, when specific instructions fail to execute correctly in the synthesized netlist (e.g., instruction 0x95bf022d), the PC and executed instruction fields remain undefined. The vulnerability is present at the hardware RTL level (or1200_genpc.v and or1200_cpu.v) and manifests only in the synthesized netlist, not in RTL simulation. An attacker or malicious firmware can trigger this by executing code sequences that update the NPC register, causing the processor to stall or execute incorrect instruction streams, compromising system integrity and availability. No patch information is currently available; this appears to be a newly discovered design issue requiring RTL correction and re-synthesis.

Affected products

  • openRISC OR1200 commit 83ac6b42d73f00daa88a996a1f6738d5a639a105

Timeline

  • 2025-01-27: disclosed: Issue reported on GitHub
  • 2026-08-26: advisory: CVE-2025-51679 published

References

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